Optimization of a CNTFET Based SRAM Cell Parameters


Sadiqul Alam Saimon, Masum Hosen Sajjad, Md Fatin Ishtiyaq, Md. Ismail Haque , Mainul Islam Mahi, Md. Shahidul Islam , Eftekhar Alam, Asifur Rahman, Md. Azad Hossain

DOI10.5110/77. 1118               Page:   05-25          Vol: 19    Issue: 03   Year: 2024

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This research proposes an optimized set of parameters for a design of the 6-T (Six Transistor CMOS SRAM) SRAM cell using CNTFET technology. The CNTFET utilized a planar gate structure with multiple cylindrical conducting channels and high k (high dielectric constant) gate dielectric material on a substrate with a different dielectric. In addition, the Stanford CNTFET model has studied, which is organized hierarchically in three main levels to simulate a MOSFET- like CNFET device. The performance of the CNTFET-based (Carbon Nano Tube Field-Effect Transistor)  SRAM (Static Random Access Memory) cell has evaluated using three main criteria: Static Noise Margin (SNM), Critical Write Time, and Standby Power. The optimization is conducted for two different voltage levels: 0.9V and 0.7V. The SNM is calculated using HSPICE simulation and the obtained data has utilized to optimize the CNTFET SRAM cell by varying  chirality and channel length. Furthermore, a comparison of the three matrices for CNTFET, CMOS, and FinFET processes is conducted. The simulation results confirm that the CNTFET SRAM design is a significant improvement in Read SNM with superior writability and lower power consumption compared to CMOS and FinFET processes. Additionally, the simulation of SNM for a wide temperature range demonstrates that the CNTFET SRAM has a relatively stable response to temperature variations.


CNTFET Cell, Optimization, Performance Matrix, SRAM Cell

Received: 09 February 2024

Accepted: 24 February 2024

Published: 02 March 2024